PMM=B_0x0, DMM=B_0x0, EN=B_0x0, TCIE=B_0x0, DMAEN=B_0x0, FMODE=B_0x0, FTIE=B_0x0, TEIE=B_0x0, FTHRES=B_0x0, APMS=B_0x0, SMIE=B_0x0, FSEL=B_0x0, ABORT=B_0x0, TCEN=B_0x0, TOIE=B_0x0
OCTOSPI control register
| EN | Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. 0 (B_0x0): OCTOSPI disabled 1 (B_0x1): OCTOSPI enabled |
| ABORT | Abort request This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. 0 (B_0x0): No abort requested 1 (B_0x1): Abort requested |
| DMAEN | DMA enable In Indirect mode, the DMA can be used to input or output data via OCTOSPI_DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation. 0 (B_0x0): DMA disabled for Indirect mode 1 (B_0x1): DMA enabled for Indirect mode |
| TCEN | Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. 0 (B_0x0): Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode. 1 (B_0x1): Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity. |
| DMM | Dual-memory configuration This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity 0 (B_0x0): Dual-quad configuration disabled 1 (B_0x1): Dual-quad configuration enabled |
| FSEL | Flash select This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected. 0 (B_0x0): FLASH 1 selected (data exchanged over IO[3:0]) 1 (B_0x1): FLASH 2 selected (data exchanged over IO[7:4]) |
| FTHRES | FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in OCTOSPI_SR, to be set. … Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value. 0 (B_0x0): FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode. 1 (B_0x1): FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode. 31 (B_0x1F): FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode. |
| TEIE | Transfer error interrupt enable This bit enables the transfer error interrupt. 0 (B_0x0): Interrupt disabled 1 (B_0x1): Interrupt enabled |
| TCIE | Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0 (B_0x0): Interrupt disabled 1 (B_0x1): Interrupt enabled |
| FTIE | FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0 (B_0x0): Interrupt disabled 1 (B_0x1): Interrupt enabled |
| SMIE | Status match interrupt enable This bit enables the status match interrupt. 0 (B_0x0): Interrupt disabled 1 (B_0x1): Interrupt enabled |
| TOIE | Timeout interrupt enable This bit enables the timeout interrupt. 0 (B_0x0): Interrupt disabled 1 (B_0x1): Interrupt enabled |
| APMS | Automatic status-polling mode stop This bit determines if the Automatic status-polling mode is stopped after a match. 0 (B_0x0): Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI. 1 (B_0x1): Automatic status-polling mode stops as soon as there is a match. |
| PMM | Polling match mode This bit indicates which method must be used to determine a match during the Automatic status-polling mode. 0 (B_0x0): AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. 1 (B_0x1): OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. |
| FMODE | Functional mode This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. 0 (B_0x0): Indirect-write mode 1 (B_0x1): Indirect-read mode 2 (B_0x2): Automatic status-polling mode 3 (B_0x3): Memory-mapped mode |