stm32 /stm32h5 /STM32H563 /PWR /PWR_BDCR

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Interpret as PWR_BDCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BREN 0 (B_0x0)MONEN 0 (B_0x0)VBE 0 (B_0x0)VBRS

VBRS=B_0x0, BREN=B_0x0, MONEN=B_0x0, VBE=B_0x0

Description

PWR Backup domain control register

Fields

BREN

Backup RAM retention in Standby and Vsub BAT/sub modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and Vsub BAT/sub modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However its content is lost in Standby and Vsub BAT/sub modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and Vsub BAT/sub modes.

0 (B_0x0): Backup RAM content lost in Standby and Vsub BAT/sub modes.

1 (B_0x1): Backup RAM content preserved in Standby and Vsub BAT/sub modes

MONEN

Backup domain voltage and temperature monitoring enable

0 (B_0x0): Backup domain voltage and temperature monitoring disabled

1 (B_0x1): Backup domain voltage and temperature monitoring enabled

VBE

Vsub BAT/sub charging enable Note: Reset only by POR,.

0 (B_0x0): Vsub BAT/sub battery charging disabled.

1 (B_0x1): Vsub BAT/sub battery charging enabled.

VBRS

Vsub BAT/sub charging resistor selection

0 (B_0x0): Charge Vsub BAT/sub through a 5 kohm resistor.

1 (B_0x1): Charge Vsub BAT/sub through a 1.5 kohm resistor.

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