TZSC1EN=B_0x0, ETHRXEN=B_0x0, CORDICEN=B_0x0, ETHTXEN=B_0x0, ETHEN=B_0x0, SRAM1EN=B_0x0, RAMCFGEN=B_0x0, CRCEN=B_0x0, FLITFEN=B_0x0, FMACEN=B_0x0, GPDMA2EN=B_0x0, GPDMA1EN=B_0x0, BKPRAMEN=B_0x0, DCACHEEN=B_0x0
RCC AHB1 peripherals clock register
| GPDMA1EN | GPDMA1 clock enable Set and reset by software. 0 (B_0x0): GPDMA1 peripheral clock disabled (default after reset) 1 (B_0x1): GPDMA1 peripheral clock enabled |
| GPDMA2EN | GPDMA2 clock enable Set and reset by software. 0 (B_0x0): GPDMA2 peripheral clock disabled (default after reset) 1 (B_0x1): GPDMA2 peripheral clock enabled |
| FLITFEN | Flash interface clock enable Set and reset by software. 0 (B_0x0): FLASH interface clock disabled 1 (B_0x1): FLASH interface clock enabled (default after reset) |
| CRCEN | CRC clock enable Set and reset by software. 0 (B_0x0): CRC peripheral clock disabled (default after reset) 1 (B_0x1): CRC peripheral clock enabled |
| CORDICEN | CORDIC clock enable Set and reset by software. 0 (B_0x0): CORDIC peripheral clock disabled (default after reset) 1 (B_0x1): CORDIC peripheral clock enabled |
| FMACEN | FMAC clock enable Set and reset by software. 0 (B_0x0): FMAC peripheral clock disabled (default after reset) 1 (B_0x1): FMAC peripheral clock enabled |
| RAMCFGEN | RAMCFG clock enable Set and reset by software. 0 (B_0x0): RAMCFG peripheral clock disabled (default after reset) 1 (B_0x1): RAMCFG peripheral clock enabled |
| ETHEN | ETH clock enable Set and reset by software 0 (B_0x0): ETH peripheral clock disabled (default after reset) 1 (B_0x1): ETH peripheral clock enabled |
| ETHTXEN | ETHTX clock enable Set and reset by software 0 (B_0x0): ETHTX clock disabled (default after reset) 1 (B_0x1): ETHTX clock enabled |
| ETHRXEN | ETHRX clock enable Set and reset by software 0 (B_0x0): ETHRX clock disabled (default after reset) 1 (B_0x1): ETHRX clock enabled |
| TZSC1EN | TZSC1 clock enable Set and reset by software 0 (B_0x0): TZSC1 peripheral clock disabled (default after reset) 1 (B_0x1): TZSC1 peripheral clock enabled |
| BKPRAMEN | BKPRAM clock enable Set and reset by software 0 (B_0x0): BKPRAM peripheral clock disabled (default after reset) 1 (B_0x1): BKPRAM peripheral clock enabled |
| DCACHEEN | DCACHE clock enable Set and reset by software 0 (B_0x0): DCACHE peripheral clock disabled (default after reset) 1 (B_0x1): DCACHE peripheral clock enabled |
| SRAM1EN | SRAM1 clock enable Set and reset by software. 0 (B_0x0): SRAM1 clock disabled 1 (B_0x1): SRAM1 clock enabled (default after reset) |