stm32 /stm32h5 /STM32H563 /RCC /RCC_AHB4LPENR

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Interpret as RCC_AHB4LPENR

SDMMC2LPEN=B_0x0, FMCLPEN=B_0x0, OCTOSPI1LPEN=B_0x0, SDMMC1LPEN=B_0x0

Description

RCC AHB4 sleep clock register

Fields

SDMMC1LPEN	SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode Set and reset by software 0 (B_0x0): SDMMC1 and SDMMC1 delay peripherals clock disabled during sleep mode 1 (B_0x1): SDMMC1 and SDMMC1 delay peripherals clock enabled during sleep mode (default after reset)
SDMMC2LPEN	SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode Set and reset by software. 0 (B_0x0): SDMMC2 and SDMMC2 delay peripherals clock disabled during sleep mode 1 (B_0x1): SDMMC2 and SDMMC2 delay peripherals clock enabled during sleep mode (default after reset)
FMCLPEN	FMC clock enable during sleep mode Set and reset by software. 0 (B_0x0): FMC peripheral clock disabled during sleep mode 1 (B_0x1): FMC peripheral clock enabled during sleep mode (default after reset)
OCTOSPI1LPEN	OCTOSPI1 clock enable during sleep mode Set and reset by software. 0 (B_0x0): OCTOSPI1 peripheral clock disabled during sleep mode 1 (B_0x1): OCTOSPI1 peripheral clock enabled during sleep mode (default after reset)

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