BOOTEN=B_0x0, BOOTMODE=B_0x0, WAITRESP=B_0x0
SDMMC command register
| CMDINDEX | Command index This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. |
| CMDTRANS | The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. |
| CMDSTOP | The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the abort signal to the DPSM when the command is sent. |
| WAITRESP | Wait for response bits This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 0 (B_0x0): No response, expect CMDSENT flag 1 (B_0x1): Short response, expect CMDREND or CCRCFAIL flag 2 (B_0x2): Short response, expect CMDREND flag (No CRC) 3 (B_0x3): Long response, expect CMDREND or CCRCFAIL flag |
| WAITINT | CPSM waits for interrupt request If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, it causes the abort of the interrupt mode. |
| WAITPEND | CPSM waits for end of data transfer (CmdPend internal signal) from DPSM This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = eMMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. |
| CPSMEN | Command path state machine (CPSM) enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command is transfered nor boot procedure is started. CPSMEN is cleared to 0. During Read Wait with SDMMC_CK stopped no command is sent and CPSMEN is kept 0. |
| DTHOLD | Hold new data block transmission and reception in the DPSM If this bit is set, the DPSM does not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. |
| BOOTMODE | Select the boot mode procedure to be used This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 0 (B_0x0): Normal boot mode procedure selected 1 (B_0x1): Alternative boot mode procedure selected. |
| BOOTEN | Enable boot mode procedure 0 (B_0x0): Boot mode procedure disabled 1 (B_0x1): Boot mode procedure enabled |
| CMDSUSPEND | The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. |