stm32 /stm32h5 /STM32H563 /TIM12 /TIM12_SMCR

Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

0 (B_0x0): Slave mode disabledif CEN = '1 then the prescaler is clocked directly by the internal clock.

1 (B_0x1): Encoder mode 1Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.

2 (B_0x2): Encoder mode 2Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level.

3 (B_0x3): Encoder mode 3Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input.

4 (B_0x4): Reset ModeRising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.

5 (B_0x5): Gated ModeThe counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

6 (B_0x6): Trigger ModeThe counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled.

7 (B_0x7): External Clock Mode 1Rising edges of the selected trigger (tim_trgi) clock the counter.

Trigger selection (see bits 21:20 for TS[4:3]) This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

0 (B_0x0): Internal trigger 0 (tim_itr0)

1 (B_0x1): Internal trigger 1 (tim_itr1)

2 (B_0x2): Internal trigger 2 (tim_itr2)

3 (B_0x3): Internal trigger 3 (tim_itr3)

4 (B_0x4): tim_ti1 edge detector (tim_ti1f_ed)

5 (B_0x5): Filtered timer input 1 (tim_ti1fp1)

6 (B_0x6): Filtered timer input 2 (tim_ti2fp2)

7 (B_0x7): External trigger input (tim_etrf)

Master/Slave mode

0 (B_0x0): No action

1 (B_0x1): The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event.

Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

0 (B_0x0): Slave mode disabledif CEN = '1 then the prescaler is clocked directly by the internal clock.

1 (B_0x1): Encoder mode 1Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.

Trigger selection (see bits 21:20 for TS[4:3]) This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

0 (B_0x0): Internal trigger 0 (tim_itr0)

1 (B_0x1): Internal trigger 1 (tim_itr1)

2 (B_0x2): Internal trigger 2 (tim_itr2)

3 (B_0x3): Internal trigger 3 (tim_itr3)