SMS=B_0x0, TS_2=B_0x0, SMS_2=B_0x0, TS=B_0x0, MSM=B_0x0
TIM15 slave mode control register
| SMS | Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Others: Reserved. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=‘00100’). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Slave mode disabledif CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 4 (B_0x4): Reset ModeRising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated ModeThe counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 6 (B_0x6): Trigger ModeThe counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled. 7 (B_0x7): External Clock Mode 1Rising edges of the selected trigger (tim_trgi) clock the counter. |
| TS | Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on tim_itrx meaning for each timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 0 (B_0x0): Internal Trigger 0 (tim_itr0) 1 (B_0x1): Internal Trigger 1 (tim_itr1) 2 (B_0x2): Internal Trigger 2 (tim_itr2) 3 (B_0x3): Internal Trigger 3 (tim_itr3) 4 (B_0x4): tim_ti1 Edge Detector (tim_ti1f_ed) 5 (B_0x5): Filtered Timer Input 1 (tim_ti1fp1) 6 (B_0x6): Filtered Timer Input 2 (tim_ti2fp2) |
| MSM | Master/slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event. |
| SMS_2 | Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Others: Reserved. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=‘00100’). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Slave mode disabledif CEN = ‘1’ then the prescaler is clocked directly by the internal clock. |
| TS_2 | Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on tim_itrx meaning for each timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 0 (B_0x0): Internal Trigger 0 (tim_itr0) 1 (B_0x1): Internal Trigger 1 (tim_itr1) 2 (B_0x2): Internal Trigger 2 (tim_itr2) 3 (B_0x3): Internal Trigger 3 (tim_itr3) |