KEYSIZE=B_0x0, DMAINEN=B_0x0, MODE=B_0x0, EN=B_0x0, CHMOD1=B_0x0, KMOD=B_0x0, CHMOD2=B_0x0, GCMPH=B_0x0, DMAOUTEN=B_0x0, NPBLB=B_0x0, DATATYPE=B_0x0
AES control register
| EN | AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DATATYPE | Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): None 1 (B_0x1): Half-word (16-bit) 2 (B_0x2): Byte (8-bit) 3 (B_0x3): Bit |
| MODE | AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): Mode 1: encryption 1 (B_0x1): Mode 2: key derivation (or key preparation for ECB/CBC decryption) 2 (B_0x2): Mode 3: decryption |
| CHMOD1 | Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): Electronic codebook (ECB) 1 (B_0x1): Cipher-block chaining (CBC) 2 (B_0x2): Counter mode (CTR) 3 (B_0x3): Galois counter mode (GCM) and Galois message authentication code (GMAC) |
| DMAINEN | DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DMAOUTEN | DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). 0 (B_0x0): Disable 1 (B_0x1): Enable |
| GCMPH | GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield). 0 (B_0x0): Init phase 1 (B_0x1): Header phase 2 (B_0x2): Payload phase 3 (B_0x3): Final phase |
| CHMOD2 | Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): Electronic codebook (ECB) 1 (B_0x1): Cipher-block chaining (CBC) |
| KEYSIZE | Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): 128 1 (B_0x1): 256 |
| NPBLB | Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: … 0 (B_0x0): All bytes are valid (no padding) 1 (B_0x1): Padding for one least-significant byte of last block 15 (B_0xF): Padding for 15 least-significant bytes of last block |
| KMOD | Key mode selection The bitfield defines how the AES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to AES_DIN and AES_DOUT registers. With selection of shared key from SAES co-processor, the AES peripheral automatically loads its key registers with the data stored in the key registers of the SAES peripheral. The key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the AES_SR register. Key error flag KEIF is set otherwise in the AES_ISR register. The bitfield must be set only when KEYSIZE is correct, and when a shared key decryption sequence has been successfully completed in SAES co-processor. N/AAttempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): Normal key 2 (B_0x2): Shared key from SAES co-processor |
| IPRST | AES peripheral software reset Setting the bit resets the AES peripheral, putting all registers to their default values, except the IPRST bit itself. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the AES to a less secure application. The bit must be low while writing any configuration registers. |