WRERR=B_0x0, KEYVALID=B_0x0, BUSY=B_0x0, RDERR=B_0x0
AES status register
| CCF | Computation completed flag This bit mirrors the CCF bit of the AES_ISR register. |
| RDERR | Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the AES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the AES_ICR register. The flag setting has no impact on the AES operation. Unexpected read returns zero. 0 (B_0x0): Not detected 1 (B_0x1): Detected |
| WRERR | Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the AES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the AES_ICR register. The flag setting has no impact on the AES operation. Unexpected write is ignored. 0 (B_0x0): Not detected 1 (B_0x1): Detected |
| BUSY | Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: When the flag indicates ‘idle’, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process. The flag is set when transferring a shared key from SAES peripheral. 0 (B_0x0): Idle 1 (B_0x1): Busy |
| KEYVALID | Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in AES_CR has been loaded in AES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the AES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by AES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the AES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the AES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to . 0 (B_0x0): No valid key information is available in key registers. EN bit in AES_CR cannot be set. 1 (B_0x1): Valid key information, defined by KEYSIZE in AES_CR, is loaded in key registers. |