TRCSTS=B_0x0
Tx queue debug register
| TXQPAUSED | Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx queue is in the Pause condition (in the Full-duplex only mode) because of the following: Reception of the PFC packet for the priorities assigned to the Tx queue when PFC is enabled Reception of 802.3x Pause packet when PFC is disabled |
| TRCSTS | MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0 (B_0x0): Idle state 1 (B_0x1): Read state (transferring data to the MAC transmitter) 2 (B_0x2): Waiting for pending Tx Status from the MAC transmitter 3 (B_0x3): Flushing the Tx queue because of the Packet Abort request from the MAC |
| TWCSTS | MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx queue Write Controller is active, and it is transferring the data to the Tx queue. |
| TXQSTS | MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx queue is not empty and some data is left for transmission. |
| TXSTSFSTS | MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission. |
| PTXQ | Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx queue. When the DTXSTS bit of Operating mode Register (ETH_MTLOMR) register is set to 1, this field does not reflect the number of packets in the Transmit queue. |
| STXSTSF | Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of status words in Tx Status FIFO. |