stm32 /stm32h5 /STM32H573 /OTFDEC1 /OTFDEC_ICR

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Interpret as OTFDEC_ICR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SEIF 0 (B_0x0)XONEIF 0 (B_0x0)KEIF

SEIF=B_0x0, KEIF=B_0x0, XONEIF=B_0x0

Description

OTFDEC interrupt clear register

Fields

SEIF

Security error interrupt flag clear This bit is written by application, and always read as 0.

0 (B_0x0): SEIF flag status is not affected.

1 (B_0x1): SEIF flag status is cleared in OTFDEC_ISR.

XONEIF

Execute-only execute-never error interrupt flag clear This bit is written by application, and always read as 0.

0 (B_0x0): XONEIF flag status is not affected.

1 (B_0x1): XONEIF flag status is cleared in OTFDEC_ISR.

KEIF

Key error interrupt flag clear This bit is written by application, and always read as 0. Note: Clearing KEIF does not solve the source of the problem (bad key registers). To be able to access again any encrypted region, OTFDEC key registers must be properly initialized again.

0 (B_0x0): KEIF flag status is not affected.

1 (B_0x1): KEIF flag status is cleared in OTFDEC_ISR.

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