stm32 /stm32h5 /STM32H573 /RCC /RCC_AHB2LPENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_AHB2LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOALPEN 0 (B_0x0)GPIOBLPEN 0 (B_0x0)GPIOCLPEN 0 (B_0x0)GPIODLPEN 0 (B_0x0)GPIOELPEN 0 (B_0x0)GPIOFLPEN 0 (B_0x0)GPIOGLPEN 0 (B_0x0)GPIOHLPEN 0 (B_0x0)GPIOILPEN 0 (B_0x0)ADC12LPEN 0 (B_0x0)DAC12LPEN 0 (B_0x0)DCMI_PSSILPEN 0 (B_0x0)AESLPEN 0 (B_0x0)HASHLPEN 0 (B_0x0)RNGLPEN 0 (B_0x0)PKALPEN 0 (B_0x0)SAESLPEN 0 (B_0x0)SRAM2LPEN 0 (B_0x0)SRAM3LPEN

GPIODLPEN=B_0x0, PKALPEN=B_0x0, HASHLPEN=B_0x0, GPIOALPEN=B_0x0, DAC12LPEN=B_0x0, ADC12LPEN=B_0x0, GPIOILPEN=B_0x0, SRAM2LPEN=B_0x0, RNGLPEN=B_0x0, SAESLPEN=B_0x0, GPIOHLPEN=B_0x0, GPIOFLPEN=B_0x0, AESLPEN=B_0x0, DCMI_PSSILPEN=B_0x0, GPIOCLPEN=B_0x0, GPIOBLPEN=B_0x0, GPIOGLPEN=B_0x0, SRAM3LPEN=B_0x0, GPIOELPEN=B_0x0

Description

RCC AHB2 sleep clock register

Fields

GPIOALPEN

GPIOA clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOA peripheral clock disabled during sleep mode

1 (B_0x1): GPIOA peripheral clock enabled during sleep mode (default after reset)

GPIOBLPEN

GPIOB clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOB peripheral clock disabled during sleep mode

1 (B_0x1): GPIOB peripheral clock enabled during sleep mode (default after reset)

GPIOCLPEN

GPIOC clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOC peripheral clock disabled during sleep mode

1 (B_0x1): GPIOC peripheral clock enabled during sleep mode (default after reset)

GPIODLPEN

GPIOD clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOD peripheral clock disabled during sleep mode

1 (B_0x1): GPIOD peripheral clock enabled during sleep mode (default after reset)

GPIOELPEN

GPIOE clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOE peripheral clock disabled during sleep mode

1 (B_0x1): GPIOE peripheral clock enabled during sleep mode (default after reset)

GPIOFLPEN

GPIOF clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOF peripheral clock disabled during sleep mode

1 (B_0x1): GPIOF peripheral clock enabled during sleep mode (default after reset)

GPIOGLPEN

GPIOG clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOG peripheral clock disabled during sleep mode

1 (B_0x1): GPIOG peripheral clock enabled during sleep mode (default after reset)

GPIOHLPEN

GPIOH clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOH peripheral clock disabled during sleep mode

1 (B_0x1): GPIOH peripheral clock enabled during sleep mode (default after reset)

GPIOILPEN

GPIOI clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPIOI peripheral clock disabled during sleep mode

1 (B_0x1): GPIOI peripheral clock enabled during sleep mode (default after reset)

ADC12LPEN

ADC1 and 2 peripherals clock enable during sleep mode Set and reset by software.

0 (B_0x0): ADC1 and 2 peripherals clock disabled during sleep mode

1 (B_0x1): ADC1 and 2 peripherals clock enabled during sleep mode (default after reset)

DAC12LPEN

DAC clock enable during sleep mode Set and reset by software.

0 (B_0x0): DAC peripheral clock disabled during sleep mode

1 (B_0x1): DAC peripheral clock enabled during sleep mode (default after reset)

DCMI_PSSILPEN

digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active) Set and reset by software.

0 (B_0x0): DCMI/PSSI peripheral clock disabled during sleep mode

1 (B_0x1): DCMI/PSSI peripheral clock enabled during sleep mode (default after reset)

AESLPEN

AES clock enable during sleep mode Set and reset by software.

0 (B_0x0): AES peripheral clock disabled during sleep mode

1 (B_0x1): AES peripheral clock enabled during sleep mode (default after reset)

HASHLPEN

HASH clock enable during sleep mode Set and reset by software.

0 (B_0x0): HASH peripheral clock disabled during sleep mode

1 (B_0x1): HASH peripheral clock enabled during sleep mode (default after reset)

RNGLPEN

RNG clock enable during sleep mode Set and reset by software.

0 (B_0x0): RNG peripheral clock disabled during sleep mode

1 (B_0x1): RNG peripheral clock enabled during sleep mode (default after reset)

PKALPEN

PKA clock enable during sleep mode Set and reset by software.

0 (B_0x0): PKA peripheral clock disabled during sleep mode

1 (B_0x1): PKA peripheral clock enabled during sleep mode (default after reset)

SAESLPEN

SAES clock enable during sleep mode Set and reset by software.

0 (B_0x0): SAES peripheral clock disabled during sleep mode

1 (B_0x1): SAES peripheral clock enabled during sleep mode (default after reset)

SRAM2LPEN

SRAM2 clock enable during sleep mode Set and reset by software.

0 (B_0x0): SRAM2 peripheral clock disabled during sleep mode

1 (B_0x1): SRAM2 peripheral clock enabled during sleep mode (default after reset)

SRAM3LPEN

SRAM3 clock enable during sleep mode Set and reset by software.

0 (B_0x0): SRAM3 peripheral clock disabled during sleep mode

1 (B_0x1): SRAM3 peripheral clock enabled during sleep mode (default after reset)

Links

()