JEXTSEL=B_0x0, JL=B_0x0, JEXTEN=B_0x0
ADC injected sequence register
| JL | Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing). 0 (B_0x0): 1 conversion 1 (B_0x1): 2 conversions 2 (B_0x2): 3 conversions 3 (B_0x3): 4 conversions |
| JEXTSEL | External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: … Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing). 0 (B_0x0): Event 0 1 (B_0x1): Event 1 2 (B_0x2): Event 2 3 (B_0x3): Event 3 4 (B_0x4): Event 4 5 (B_0x5): Event 5 6 (B_0x6): Event 6 7 (B_0x7): Event 7 31 (B_0x1F): Event 31: |
| JEXTEN | External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing). If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions) 0 (B_0x0): If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled and 1 (B_0x1): Hardware trigger detection on the rising edge 2 (B_0x2): Hardware trigger detection on the falling edge 3 (B_0x3): Hardware trigger detection on both the rising and falling edges |
| JSQ1 | 1st conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register). |
| JSQ2 | 2nd conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register). |
| JSQ3 | 3rd conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register). |
| JSQ4 | 4th conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register). |