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stm32 /stm32h7 /STM32H723 /RCC /D3CFGR

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Interpret as D3CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0D3PPRE

Description

RCC Domain 3 Clock Configuration Register

Fields

D3PPRE

D3 domain APB4 prescaler

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32