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stm32 /stm32h7 /STM32H723 /SPDIFRX /FMT0_DR

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Interpret as FMT0_DR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DR0 (PE)PE 0 (V)V0 (U)U0 (C)C0PT

Description

Data input register

Fields

DR

Parity Error bit
PE

Parity Error bit
V

Validity bit
U

User bit
C

Channel Status bit
PT

Preamble Type

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32