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stm32 /stm32h7 /STM32H742 /DBGMCU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBGSLEEP_D1)DBGSLEEP_D1 0 (DBGSTOP_D1)DBGSTOP_D1 0 (DBGSTBY_D1)DBGSTBY_D1 0 (DBGSLEEP_D2)DBGSLEEP_D2 0 (DBGSTOP_D2)DBGSTOP_D2 0 (DBGSTBY_D2)DBGSTBY_D2 0 (DBGSTOP_D3)DBGSTOP_D3 0 (DBGSTBY_D3)DBGSTBY_D3 0 (TRACECLKEN)TRACECLKEN 0 (D1DBGCKEN)D1DBGCKEN 0 (D3DBGCKEN)D3DBGCKEN 0 (TRGOEN)TRGOEN

Description

DBGMCU Configuration Register

Fields

DBGSLEEP_D1

Allow D1 domain debug in Sleep mode
DBGSTOP_D1

Allow D1 domain debug in Stop mode
DBGSTBY_D1

Allow D1 domain debug in Standby mode
DBGSLEEP_D2

Allow D2 domain debug in Sleep mode
DBGSTOP_D2

Allow D2 domain debug in Stop mode
DBGSTBY_D2

Allow D2 domain debug in Standby mode
DBGSTOP_D3

Allow debug in D3 Stop mode
DBGSTBY_D3

Allow debug in D3 Standby mode
TRACECLKEN

Trace port clock enable
D1DBGCKEN

D1 debug clock enable
D3DBGCKEN

D3 debug clock enable
TRGOEN

External trigger output enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32