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stm32 /stm32h7 /STM32H750 /ETH /ETH_MMC_TX_INTERRUPT

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Interpret as ETH_MMC_TX_INTERRUPT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXSCOLGPIS)TXSCOLGPIS 0 (TXMCOLGPIS)TXMCOLGPIS 0 (TXGPKTIS)TXGPKTIS 0 (TXLPIUSCIS)TXLPIUSCIS 0 (TXLPITRCIS)TXLPITRCIS

Description

MMC Tx interrupt register

Fields

TXSCOLGPIS

MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the (ETH_TX_SINGLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value.
TXMCOLGPIS

MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the (ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS) counter reaches half of the maximum value or the maximum value.
TXGPKTIS

MMC Transmit Good Packet Counter Interrupt Status This bit is set when the counter reaches half of the maximum value or the maximum value.
TXLPIUSCIS

MMC Transmit LPI microsecond counter interrupt status This bit is set when the counter reaches half of the maximum value or the maximum value.
TXLPITRCIS

MMC Transmit LPI transition counter interrupt status This bit is set when the counter reaches half of the maximum value or the maximum value.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32