stm32 /stm32h7 /STM32H7A3 /Flash /FLASH_CR1

Bank 1 configuration lock bit This bit locks the FLASH_CR1 register. The correct write sequence to FLASH_KEYR1 register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_KEYR1 is performed twice, this bit remains locked until the next system reset. LOCK1 can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK1 changes from 0 to 1, the other bits of FLASH_CR1 register do not change.

0 (B_0x0): FLASH_CR1 register unlocked

1 (B_0x1): FLASH_CR1 register locked

Bank 1 internal buffer control bit Setting PG1 bit to 1 enables internal buffer for write operations to bank 1. This allows preparing program operations even if a sector or bank erase is ongoing. PG1 can be programmed only when LOCK1 is cleared to 0. When PG1 is reset, the internal buffer is disabled for write operations to bank 1, and all the data stored in the buffer but not sent to the operation queue are lost.

0 (B_0x0): Internal buffer disabled for write operations to bank 1

1 (B_0x1): Internal buffer enabled for write operations to bank 1

Bank 1 sector erase request Setting SER1 bit to 1 requests a sector erase on bank 1. SER1 can be programmed only when LOCK1 is cleared to 0. BER1 has a higher priority than SER1: if both bits are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a sector erase is required on a protected sector.

0 (B_0x0): sector erase not requested on bank 1

1 (B_0x1): sector erase requested on bank 1

Bank 1 erase request Setting BER1 bit to 1 requests a bank erase operation on bank 1 (user Flash memory only). BER1 can be programmed only when LOCK1 is cleared to 0. BER1 has a higher priority than SER1: if both are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a bank erase is required and some sectors are protected.

0 (B_0x0): bank erase not requested on bank 1

1 (B_0x1): bank erase requested on bank 1

Bank 1 write forcing control bit FW1 forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW1 can be programmed only when LOCK1 is cleared to 0. The embedded Flash memory resets FW1 when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW1 does not start several write operations when the force-write operations are performed consecutively).

Bank 1 erase start control bit START1 bit is used to start a sector erase or a bank erase operation. START1 can be programmed only when LOCK1 is cleared to 0. The embedded Flash memory resets START1 when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged.

Bank 1 sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SSN1 can be programmed only when LOCK1 is cleared to 0. … … … Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively.

0 (B_0x0): Sector 0 of user Flash bank 1 selected

1 (B_0x1): Sector 1 of user Flash bank 1 selected

15 (B_0xF): Sector 15 of user Flash bank 1 selected

63 (B_0x3F): Sector 63 of user Flash bank 1 selected

127 (B_0x7F): Sector 127 of user Flash bank 1 selected

Bank 1 CRC control bit Setting CRC_EN bit to 1 enables the CRC calculation on bank 1. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR1 register. When CRC calculation is performed on bank 1, it can only be disabled by setting CRC_EN bit to 0. Resetting CRC_EN clears CRC configuration and resets the content of FLASH_CRCDATAR register. Clearing CRC_EN to 0 sets CRCDATA to 0x0. CRC_EN can be programmed only when LOCK1 is cleared to 0.

Bank 1 end-of-program interrupt control bit Setting EOPIE1 bit to 1 enables the generation of an interrupt at the end of a program operation to bank 1. EOPIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated at the end of a program operation to bank 1.

1 (B_0x1): interrupt enabled when at the end of a program operation to bank 1.

Bank 1 write protection error interrupt enable bit When WRPERRIE1 bit is set to 1, an interrupt is generated when a protection error occurs during a program operation to bank 1. WRPERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a protection error occurs on bank 1

1 (B_0x1): interrupt generated when a protection error occurs on bank 1.

Bank 1 programming sequence error interrupt enable bit When PGSERRIE1 bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation to bank 1. PGSERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a sequence error occurs on bank 1

1 (B_0x1): interrupt generated when sequence error occurs on bank 1.

Bank 1 strobe error interrupt enable bit When STRBERRIE1 bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation to bank 1. STRBERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a strobe error occurs on bank 1

1 (B_0x1): interrupt generated when strobe error occurs on bank 1.

Bank 1 inconsistency error interrupt enable bit When INCERRIE1 bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation to bank 1. INCERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a inconsistency error occurs on bank 1

1 (B_0x1): interrupt generated when a inconsistency error occurs on bank 1.

Bank 1 read protection error interrupt enable bit When RDPERRIE1 bit is set to 1, an interrupt is generated when a read protection error occurs (access to an address protected by PCROP or by RDP level 1) during a read operation from bank 1. RDPERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a read protection error occurs on bank 1

1 (B_0x1): an interrupt is generated when a read protection error occurs on bank 1

Bank 1 secure error interrupt enable bit When RDSERRIE1 bit is set to 1, an interrupt is generated when a secure error (access to a secure-only protected address) occurs during a read operation from bank 1. RDSERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a secure error occurs on bank 1

1 (B_0x1): an interrupt is generated when a secure error occurs on bank 1

Bank 1 ECC single correction error interrupt enable bit When SNECCERRIE1 bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation from bank 1. SNECCERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when an ECC single correction error occurs on bank 1

1 (B_0x1): interrupt generated when an ECC single correction error occurs on bank 1

Bank 1 ECC double detection error interrupt enable bit When DBECCERRIE1 bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a read operation from bank 1. DBECCERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when an ECC double detection error occurs on bank 1

1 (B_0x1): interrupt generated if an ECC double detection error occurs on bank 1

Bank 1 CRC end of calculation interrupt enable bit When CRCENDIE1 bit is set to 1, an interrupt is generated when the CRC computation has completed on bank 1. CRCENDIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when CRC computation complete on bank 1

1 (B_0x1): interrupt generated when CRC computation complete on bank 1

Bank 1 CRC read error interrupt enable bit When CRCRDERRIE1 bit is set to 1, an interrupt is generated when a protected area (PCROP or secure-only) has been detected during the last CRC computation on bank 1. CRCRDERRIE1 can be programmed only when LOCK1 is cleared to 0.

0 (B_0x0): no interrupt generated when a CRC read error occurs on bank 1

1 (B_0x1): interrupt generated when a CRC read error occurs on bank 1