This register allows controlling CPU1 power.
| RETDS_CD | RETDS_CD |
| PDDS_SRD | PDDS_SRD |
| STOPF | STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. |
| SBF | System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit |
| CSSF | Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware. |
| RUN_SRD | RUN_SRD |