DMA1EN=B_0x0, CRCEN=B_0x0, ADC12EN=B_0x0, USB1OTGEN=B_0x0, DMA2EN=B_0x0, USB1ULPIEN=B_0x0
| DMA1EN | DMA1 clock enable Set and reset by software. 0 (B_0x0): DMA1 clock disabled (default after reset) 1 (B_0x1): DMA1 clock enabled |
| DMA2EN | DMA2 clock enable Set and reset by software. 0 (B_0x0): DMA2 clock disabled (default after reset) 1 (B_0x1): DMA2 clock enabled |
| ADC12EN | ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock. 0 (B_0x0): ADC1 and 2 peripheral clocks disabled (default after reset) 1 (B_0x1): ADC1 and 2 peripheral clocks enabled |
| CRCEN | CRC peripheral clock enable Set and reset by software. 0 (B_0x0): CRC peripheral clock disabled (default after reset) 1 (B_0x1): CRC peripheral clock enabled |
| USB1OTGEN | USB1OTG peripheral clocks enable Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock. 0 (B_0x0): USB1OTG peripheral clocks disabled (default after reset) 1 (B_0x1): USB1OTG peripheral clocks enabled |
| USB1ULPIEN | USB_PHY1 clocks enable Set and reset by software. 0 (B_0x0): USB1ULPI PHY clocks disabled (default after reset) 1 (B_0x1): USB1ULPI PHY clocks enabled |