DTCM2LPEN=B_0x0, FLITFLPEN=B_0x0, GFXMMULPEN=B_0x0, MDMALPEN=B_0x0, AXISRAM3LPEN=B_0x0, OCTOSPIMLPEN=B_0x0, DTCM1LPEN=B_0x0, OTFD2LPEN=B_0x0, OCTOSPI2LPEN=B_0x0, AXISRAM1LPEN=B_0x0, AXISRAM2LPEN=B_0x0, SDMMC1LPEN=B_0x0, OCTOSPI1LPEN=B_0x0, DMA2DLPEN=B_0x0, JPGDECLPEN=B_0x0, ITCMLPEN=B_0x0, OTFD1LPEN=B_0x0, FMCLPEN=B_0x0
| MDMALPEN | MDMA clock enable during CSleep mode Set and reset by software. 0 (B_0x0): MDMA peripheral clock disabled during CSleep mode 1 (B_0x1): MDMA peripheral clock enabled during CSleep mode (default after reset) |
| DMA2DLPEN | DMA2D clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DMA2D peripheral clock disabled during CSleep mode 1 (B_0x1): DMA2D peripheral clock enabled during CSleep mode (default after reset) |
| JPGDECLPEN | JPGDEC clock enable during CSleep mode Set and reset by software. 0 (B_0x0): JPGDEC peripheral clock disabled during CSleep mode 1 (B_0x1): JPGDEC peripheral clock enabled during CSleep mode (default after reset) |
| FLITFLPEN | FLITF clock enable during CSleep mode Set and reset by software. 0 (B_0x0): FLITF clock disabled during CSleep mode 1 (B_0x1): FLITF clock enabled during CSleep mode (default after reset) |
| FMCLPEN | FMC peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock. 0 (B_0x0): FMC peripheral clocks disabled during CSleep mode 1 (B_0x1): FMC peripheral clocks enabled during CSleep mode (default after reset): |
| OCTOSPI1LPEN | OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode Set and reset by software. 0 (B_0x0): OCTOSPI1 and OCTOSPI1 delay clock disabled during CSleep mode 1 (B_0x1): OCTOSPI1 and OCTOSPI1 delay clock enabled during CSleep mode (default after reset) |
| SDMMC1LPEN | SDMMC1 and SDMMC1 delay clock enable during CSleep mode Set and reset by software. 0 (B_0x0): SDMMC1 and SDMMC1 delay clock disabled during CSleep mode 1 (B_0x1): SDMMC1 and SDMMC1 delay clock enabled during CSleep mode (default after reset) |
| OCTOSPI2LPEN | OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode Set and reset by software. 0 (B_0x0): OCTOSPI2 and OCTOSPI2 delay clock disabled during CSleep mode 1 (B_0x1): OCTOSPI2 and OCTOSPI2 delay clock enabled during CSleep mode (default after reset) |
| OCTOSPIMLPEN | OCTOSPIM block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): OCTOSPIM interface clock disabled during CSleep mode 1 (B_0x1): OCTOSPIM interface clock enabled during CSleep mode (default after reset) |
| OTFD1LPEN | OTFD1 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): OTFD1 interface clock disabled during CSleep mode 1 (B_0x1): OTFD1 interface clock enabled during CSleep mode (default after reset) |
| OTFD2LPEN | OTFD2 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): OTFD2 interface clock disabled during CSleep mode 1 (B_0x1): OTFD2 interface clock enabled during CSleep mode (default after reset) |
| GFXMMULPEN | GFXMMU block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): GFXMMU interface clock disabled during CSleep mode 1 (B_0x1): GFXMMU interface clock enabled during CSleep mode (default after reset) |
| AXISRAM2LPEN | AXISRAM2 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): AXISRAM2 interface clock disabled during CSleep mode 1 (B_0x1): AXISRAM2 interface clock enabled during CSleep mode (default after reset) |
| AXISRAM3LPEN | AXISRAM3 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): AXISRAM3 interface clock disabled during CSleep mode 1 (B_0x1): AXISRAM3 interface clock enabled during CSleep mode (default after reset) |
| DTCM1LPEN | DTCM1 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DTCM1 interface clock disabled during CSleep mode 1 (B_0x1): DTCM1 interface clock enabled during CSleep mode (default after reset) |
| DTCM2LPEN | DTCM2 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DTCM2 interface clock disabled during CSleep mode 1 (B_0x1): DTCM2 interface clock enabled during CSleep mode (default after reset) |
| ITCMLPEN | ITCM block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): ITCM interface clock disabled during CSleep mode 1 (B_0x1): ITCM interface clock enabled during CSleep mode (default after reset) |
| AXISRAM1LPEN | AXISRAM1 block clock enable during CSleep mode Set and reset by software. 0 (B_0x0): AXISRAM1 interface clock disabled during CSleep mode 1 (B_0x1): AXISRAM1 interface clock enabled during CSleep mode (default after reset) |