stm32 /stm32h7 /STM32H7A3 /RCC /RCC_AHB4LPENR

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Interpret as RCC_AHB4LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOALPEN 0 (B_0x0)GPIOBLPEN 0 (B_0x0)GPIOCLPEN 0 (B_0x0)GPIODLPEN 0 (B_0x0)GPIOELPEN 0 (B_0x0)GPIOFLPEN 0 (B_0x0)GPIOGLPEN 0 (B_0x0)GPIOHLPEN 0 (B_0x0)GPIOILPEN 0 (B_0x0)GPIOJLPEN 0 (B_0x0)GPIOKLPEN 0 (B_0x0)BDMA2LPEN 0 (B_0x0)BKPRAMLPEN 0 (B_0x0)SRDSRAMLPEN

SRDSRAMLPEN=B_0x0, GPIOBLPEN=B_0x0, GPIOJLPEN=B_0x0, BDMA2LPEN=B_0x0, GPIOFLPEN=B_0x0, GPIODLPEN=B_0x0, GPIOALPEN=B_0x0, GPIOCLPEN=B_0x0, GPIOILPEN=B_0x0, BKPRAMLPEN=B_0x0, GPIOKLPEN=B_0x0, GPIOHLPEN=B_0x0, GPIOGLPEN=B_0x0, GPIOELPEN=B_0x0

Fields

GPIOALPEN

GPIOA peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOA peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOA peripheral clock enabled during CSleep mode (default after reset)

GPIOBLPEN

GPIOB peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOB peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOB peripheral clock enabled during CSleep mode (default after reset)

GPIOCLPEN

GPIOC peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOC peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOC peripheral clock enabled during CSleep mode (default after reset)

GPIODLPEN

GPIOD peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOD peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOD peripheral clock enabled during CSleep mode (default after reset)

GPIOELPEN

GPIOE peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOE peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOE peripheral clock enabled during CSleep mode (default after reset)

GPIOFLPEN

GPIOF peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOF peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOF peripheral clock enabled during CSleep mode (default after reset)

GPIOGLPEN

GPIOG peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOG peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOG peripheral clock enabled during CSleep mode (default after reset)

GPIOHLPEN

GPIOH peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOH peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOH peripheral clock enabled during CSleep mode (default after reset)

GPIOILPEN

GPIOI peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOI peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOI peripheral clock enabled during CSleep mode (default after reset)

GPIOJLPEN

GPIOJ peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOJ peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOJ peripheral clock enabled during CSleep mode (default after reset)

GPIOKLPEN

GPIOK peripheral clock enable during CSleep mode Set and reset by software.

0 (B_0x0): GPIOK peripheral clock disabled during CSleep mode

1 (B_0x1): GPIOK peripheral clock enabled during CSleep mode (default after reset)

BDMA2LPEN

SmartRun domain DMA and DMAMUX clock enable during CSleep mode Set and reset by software.

0 (B_0x0): BDMA2 and DMAMUX2 clock disabled during CSleep mode

1 (B_0x1): BDMA2 and DMAMUX2 clock enabled during CSleep mode (default after reset)

BKPRAMLPEN

Backup RAM clock enable during CSleep mode Set and reset by software.

0 (B_0x0): Backup RAM clock disabled during CSleep mode

1 (B_0x1): Backup RAM clock enabled during CSleep mode (default after reset)

SRDSRAMLPEN

SmartRun domain SRAM clock enable during CSleep mode Set and reset by software.

0 (B_0x0): SRDSRAM clock disabled during CSleep mode

1 (B_0x1): SRDSRAM clock enabled during CSleep mode (default after reset)

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