DAC1LPEN=B_0x0, I2C1LPEN=B_0x0, SPI3LPEN=B_0x0, USART2LPEN=B_0x0, I2C3LPEN=B_0x0, TIM4LPEN=B_0x0, TIM14LPEN=B_0x0, SPI2LPEN=B_0x0, I2C2LPEN=B_0x0, UART8LPEN=B_0x0, CECLPEN=B_0x0, TIM12LPEN=B_0x0, TIM6LPEN=B_0x0, UART5LPEN=B_0x0, UART4LPEN=B_0x0, TIM5LPEN=B_0x0, TIM3LPEN=B_0x0, LPTIM1LPEN=B_0x0, SPDIFRXLPEN=B_0x0, TIM7LPEN=B_0x0, UART7LPEN=B_0x0, USART3LPEN=B_0x0, TIM13LPEN=B_0x0, TIM2LPEN=B_0x0
| TIM2LPEN | TIM2 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM2 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM2 peripheral clock enabled during CSleep mode (default after reset) |
| TIM3LPEN | TIM3 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM3 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM3 peripheral clock enabled during CSleep mode (default after reset) |
| TIM4LPEN | TIM4 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM4 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM4 peripheral clock enabled during CSleep mode (default after reset) |
| TIM5LPEN | TIM5 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM5 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM5 peripheral clock enabled during CSleep mode (default after reset) |
| TIM6LPEN | TIM6 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM6 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM6 peripheral clock enabled during CSleep mode (default after reset) |
| TIM7LPEN | TIM7 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM7 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM7 peripheral clock enabled during CSleep mode (default after reset) |
| TIM12LPEN | TIM12 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM12 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM12 peripheral clock enabled during CSleep mode (default after reset) |
| TIM13LPEN | TIM13 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM13 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM13 peripheral clock enabled during CSleep mode (default after reset) |
| TIM14LPEN | TIM14 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM14 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM14 peripheral clock enabled during CSleep mode (default after reset) |
| LPTIM1LPEN | LPTIM1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): LPTIM1 peripheral clocks disabled during CSleep mode 1 (B_0x1): LPTIM1 peripheral clocks enabled during CSleep mode (default after reset) |
| SPI2LPEN | SPI2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): SPI2 peripheral clocks disabled during CSleep mode 1 (B_0x1): SPI2 peripheral clocks enabled during CSleep mode (default after reset) |
| SPI3LPEN | SPI3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): SPI3 peripheral clocks disabled during CSleep mode 1 (B_0x1): SPI3 peripheral clocks enabled during CSleep mode (default after reset) |
| SPDIFRXLPEN | SPDIFRX peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): SPDIFRX peripheral clocks disabled during CSleep mode 1 (B_0x1): SPDIFRX peripheral clocks enabled during CSleep mode (default after reset) |
| USART2LPEN | USART2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): USART2 peripheral clocks disabled during CSleep mode 1 (B_0x1): USART2 peripheral clocks enabled during CSleep mode (default after reset) |
| USART3LPEN | USART3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): USART3 peripheral clocks disabled during CSleep mode 1 (B_0x1): USART3 peripheral clocks enabled during CSleep mode (default after reset): |
| UART4LPEN | UART4 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): UART4 peripheral clocks disabled during CSleep mode 1 (B_0x1): UART4 peripheral clocks enabled during CSleep mode (default after reset) |
| UART5LPEN | UART5 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): UART5 peripheral clocks disabled during CSleep mode 1 (B_0x1): UART5 peripheral clocks enabled during CSleep mode (default after reset) |
| I2C1LPEN | I2C1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): I2C1 peripheral clocks disabled during CSleep mode 1 (B_0x1): I2C1 peripheral clocks enabled during CSleep mode (default after reset): |
| I2C2LPEN | I2C2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): I2C2 peripheral clocks disabled during CSleep mode 1 (B_0x1): I2C2 peripheral clocks enabled during CSleep mode (default after reset): |
| I2C3LPEN | I2C3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): I2C3 peripheral clocks disabled during CSleep mode 1 (B_0x1): I2C3 peripheral clocks enabled during CSleep mode (default after reset): |
| CECLPEN | HDMI-CEC peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): HDMI-CEC peripheral clocks disabled during CSleep mode 1 (B_0x1): HDMI-CEC peripheral clocks enabled during CSleep mode (default after reset) |
| DAC1LPEN | DAC1 (containing two converters) peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DAC1 peripheral clock disabled during CSleep mode 1 (B_0x1): DAC1 peripheral clock enabled during CSleep mode (default after reset) |
| UART7LPEN | UART7 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): UART7 peripheral clocks disabled during CSleep mode 1 (B_0x1): UART7 peripheral clocks enabled during CSleep mode (default after reset): |
| UART8LPEN | UART8 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): UART8 peripheral clocks disabled during CSleep mode 1 (B_0x1): UART8 peripheral clocks enabled during CSleep mode (default after reset): |