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stm32 /stm32h7 /STM32H7A3 /RCC /RCC_SRDCFGR

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Interpret as RCC_SRDCFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SRDPPRE

Fields

SRDPPRE

SmartRun domain APB4 prescaler Set and reset by software to control the SmartRun domain APB4 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk4 after SRDPPRE write. 0xx: rcc_pclk4 = rcc_hclk4 (default after reset)

4 (B_0x4): rcc_pclk4 = rcc_hclk4 / 2

5 (B_0x5): rcc_pclk4 = rcc_hclk4 / 4

6 (B_0x6): rcc_pclk4 = rcc_hclk4 / 8

7 (B_0x7): rcc_pclk4 = rcc_hclk4 / 16

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32