Regviz

stm32 /stm32h7 /STM32H7B0 /BDMA2 /BDMA_CM1AR5

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Interpret as BDMA_CM1AR5

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https://regviz.com/r/stm32/stm32h7/STM32H7B0/BDMA2/BDMA_CM1AR5#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Description

This register must not be written when the channel is enabled.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32