CRYPTEN=B_0x0, AHBSRAM1EN=B_0x0, SDMMC2EN=B_0x0, HSEMEN=B_0x0, AHBSRAM2EN=B_0x0, BDMA1EN=B_0x0, DCMI_PSSIEN=B_0x0, RNGEN=B_0x0, HASHEN=B_0x0
| DCMI_PSSIEN | digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active) Set and reset by software. 0 (B_0x0): DCMI/PSSI peripheral clock disabled (default after reset) 1 (B_0x1): DCMI/PSSI peripheral clock enabled |
| HSEMEN | HSEM peripheral clock enable Set and reset by software. 0 (B_0x0): HSEM peripheral clock disabled (default after reset) 1 (B_0x1): HSEM peripheral clock enabled |
| CRYPTEN | CRYPT peripheral clock enable Set and reset by software. 0 (B_0x0): CRYPT peripheral clock disabled (default after reset) 1 (B_0x1): CRYPT peripheral clock enabled |
| HASHEN | HASH peripheral clock enable Set and reset by software. 0 (B_0x0): HASH peripheral clock disabled (default after reset) 1 (B_0x1): HASH peripheral clock enabled |
| RNGEN | RNG peripheral clocks enable Set and reset by software. The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock. 0 (B_0x0): RNG peripheral clocks disabled (default after reset) 1 (B_0x1): RNG peripheral clocks enabled: |
| SDMMC2EN | SDMMC2 and SDMMC2 delay clock enable Set and reset by software. 0 (B_0x0): SDMMC2 and SDMMC2 delay clock disabled (default after reset) 1 (B_0x1): SDMMC2 and SDMMC2 delay clock enabled |
| BDMA1EN | DMA clock enable (DFSDM dedicated DMA) Set and reset by software. 0 (B_0x0): DMA clock disabled (default after reset) 1 (B_0x1): DMA clock enabled |
| AHBSRAM1EN | AHBSRAM1 block enable Set and reset by software. When set, this bit indicates that the SRAM1 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun. 0 (B_0x0): AHBSRAM1 interface clock is disabled. (default after reset) 1 (B_0x1): AHBSRAM1 interface clock is enabled. |
| AHBSRAM2EN | AHBSRAM2 block enable Set and reset by software. When set, this bit indicates that the SRAM2 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun. 0 (B_0x0): AHBSRAM2 interface clock is disabled. (default after reset) 1 (B_0x1): AHBSRAM2 interface clock is enabled. |