AHBSRAM2LPEN=B_0x0, SDMMC2LPEN=B_0x0, DCMI_PSSILPEN=B_0x0, AHBSRAM1LPEN=B_0x0, RNGLPEN=B_0x0, DFSDMDMALPEN=B_0x0, HASHLPEN=B_0x0, CRYPTLPEN=B_0x0
| DCMI_PSSILPEN | digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active) Set and reset by software. 0 (B_0x0): DCMI/PSSI peripheral clock disabled during CSleep mode 1 (B_0x1): DCMI/PSSI peripheral clock enabled during CSleep mode (default after reset) |
| CRYPTLPEN | CRYPT peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): CRYPT peripheral clock disabled during CSleep mode 1 (B_0x1): CRYPT peripheral clock enabled during CSleep mode (default after reset) |
| HASHLPEN | HASH peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): HASH peripheral clock disabled during CSleep mode 1 (B_0x1): HASH peripheral clock enabled during CSleep mode (default after reset) |
| RNGLPEN | RNG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock. 0 (B_0x0): RNG peripheral clocks disabled during CSleep mode 1 (B_0x1): RNG peripheral clock enabled during CSleep mode (default after reset) |
| SDMMC2LPEN | SDMMC2 and SDMMC2 delay clock enable during CSleep mode Set and reset by software. 0 (B_0x0): SDMMC2 and SDMMC2 delay clock disabled during CSleep mode 1 (B_0x1): SDMMC2 and SDMMC2 delay clock enabled during CSleep mode (default after reset) |
| DFSDMDMALPEN | DFSDMDMA clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DFSDMDMA clock disabled during CSleep mode 1 (B_0x1): DFSDMDMA clock enabled during CSleep mode (default after reset) |
| AHBSRAM1LPEN | AHBSRAM1 clock enable during CSleep mode Set and reset by software. 0 (B_0x0): AHBSRAM1 clock disabled during CSleep mode 1 (B_0x1): AHBSRAM1 clock enabled during CSleep mode (default after reset) |
| AHBSRAM2LPEN | AHBSRAM2 clock enable during CSleep mode Set and reset by software. 0 (B_0x0): AHBSRAM2 clock disabled during CSleep mode 1 (B_0x1): AHBSRAM2 clock enabled during CSleep mode (default after reset) |