LTDCEN=B_0x0, WWDGEN=B_0x0
| LTDCEN | LTDC clock enable Provides the clock (ltdc_pclk, ltdc_aclk, ltdc_ker_ck) to the LTDC block. Set and reset by software. 0 (B_0x0): LTDC peripheral clock disabled (default after reset) 1 (B_0x1): LTDC peripheral clock provided to the LTDC block |
| WWDGEN | WWDG clock enable Set by software, and reset by hardware when a system reset occurs. Note that in order to work properly, before enabling the WWDG, the bit WW1RSC must be set to 1. 0 (B_0x0): WWDG peripheral clock disable (default after reset) 1 (B_0x1): WWDG peripheral clock enabled |