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stm32 /stm32h7rs /STM32H7R /ADC1 /ADC_OR

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Interpret as ADC_OR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OP0

OP0=B_0x0

Description

ADC option register

Fields

OP0

Option bit 0

0 (B_0x0): VDDCORE channel disabled

1 (B_0x1): VDDCORE channel enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32