SMP8=B_0x0, SMP1=B_0x0, SMP7=B_0x0, SMP4=B_0x0, SMP9=B_0x0, SMP0=B_0x0, SMPPLUS=B_0x0, SMP2=B_0x0, SMP3=B_0x0, SMP5=B_0x0, SMP6=B_0x0
ADC sample time register 1
| SMP0 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP1 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP2 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP3 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP4 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP5 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP6 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP7 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP8 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP9 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMPPLUS | Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0. 0 (B_0x0): The sampling time remains set to 2.5 ADC clock cycles remains 1 (B_0x1): 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers. |