CCKDIV=B_0x0, CCK0DIR=B_0x0, PROCDIV=B_0x0, CCK1EN=B_0x0, CCK1DIR=B_0x0, CKGMOD=B_0x0, TRGSENS=B_0x0, CKGACTIVE=B_0x0, CCK0EN=B_0x0, CKGDEN=B_0x0
ADF clock generator control register
| CKGDEN | CKGEN dividers enable This bit is set and reset by software. It is used to enable/disable the clock dividers of the CKGEN: PROCDIV and CCKDIV. 0 (B_0x0): CKGEN dividers disabled 1 (B_0x1): CKGEN dividers enabled |
| CCK0EN | ADF_CCK0 clock enable This bit is set and reset by software. It is used to control the generation of the bitstream clock on the ADF_CCK0 pin. 0 (B_0x0): Bitstream clock not generated 1 (B_0x1): Bitstream clock generated on the ADF_CCK0 pin |
| CCK1EN | ADF_CCK1 clock enable This bit is set and reset by software. It is used to control the generation of the bitstream clock on the ADF_CCK1 pin. 0 (B_0x0): Bitstream clock not generated 1 (B_0x1): Bitstream clock generated on the ADF_CCK1 pin. |
| CKGMOD | Clock generator mode This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): The kernel clock is provided to the dividers as soon as CKGDEN is set to 1. 1 (B_0x1): The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met. |
| CCK0DIR | ADF_CCK0 direction This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): The ADF_CCK0 pin direction is in input. 1 (B_0x1): The ADF_CCK0 pin direction is in output. |
| CCK1DIR | ADF_CCK1 direction This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. Note: This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): The ADF_CCK1 pin direction is in input. 1 (B_0x1): The ADF_CCK1 pin direction is in output. |
| TRGSENS | CKGEN trigger sensitivity selection This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. Note: When the trigger source is TRGO, the sensitivity is forced to falling edge, thus TRGSENS value is not taken into account. This bit can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): A rising edge event triggers the activation of CKGEN dividers. 1 (B_0x1): A falling edge even triggers the activation of CKGEN dividers. |
| TRGSRC | Digital filter trigger signal selection This field is set and cleared by software. It is used to select which external signals trigger the corresponding filter. This field is not significant if the CKGMOD = 0. 000x: TRGO selected others: reserved Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 2 (B_0x2): adf_trg1 selected |
| CCKDIV | Divider to control the ADF_CCK clock This field is set and reset by software. It is used to adjust the frequency of the ADF_CCK clock. The input clock of this divider is the clock provided to the SITF. More globally, the frequency of the ADF_CCK is given by the following formula: This field must not be changed if the filter is enabled (DFTEN = 1). … Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): The ADF_CCK clock is adf_proc_ck. 1 (B_0x1): The ADF_CCK clock is adf_proc_ck / 2. 2 (B_0x2): The ADF_CCK clock is adf_proc_ck / 3. 15 (B_0xF): The ADF_CCK clock is adf_proc_ck / 16. |
| PROCDIV | Divider to control the serial interface clock this field is set and reset by software. It is used to adjust the frequency of the clock provided to the SITF. This field must not be changed if the filter is enabled (DFTEN = 1). … Note: This field can be write-protected (see Section 46.4.13: Register protection for details). 0 (B_0x0): adf_ker_ck provided to the SITF 1 (B_0x1): adf_ker_ck / 2 provided to the SITF |
| CKGACTIVE | Clock generator active flag This bit is set and cleared by hardware. Ii is used by the application to check if the clock generator is effectively enabled (active) or not. The protected fields of this function can only be updated when CKGACTIVE = 0 (see Section 46.4.13: Register protection for details). The delay between a transition on CKGDEN and a transition on CKGACTIVE is two periods of AHB clock and two 2 periods of adf_proc_ck. 0 (B_0x0): The clock generator is not active and can be configured if needed. 1 (B_0x1): The clock generator is active and protected fields cannot be configured. |