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stm32 /stm32h7rs /STM32H7R /DBGMCU /DBGMCU_APB4FZR

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Interpret as DBGMCU_APB4FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LPTIM2 0 (B_0x0)LPTIM3 0 (B_0x0)LPTIM4 0 (B_0x0)LPTIM5 0 (B_0x0)RTC 0 (B_0x0)IWDG

RTC=B_0x0, LPTIM5=B_0x0, LPTIM3=B_0x0, IWDG=B_0x0, LPTIM2=B_0x0, LPTIM4=B_0x0

Description

DBGMCU APB4 peripheral freeze register

Fields

LPTIM2

LPTIM2 stop in debug

0 (B_0x0): Normal operation - LPTIM2 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - LPTIM2 is frozen while Cortex-M7 is in Debug mode
LPTIM3

LPTIM2 stop in debug

0 (B_0x0): Normal operation - LPTIM2 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - LPTIM2 is frozen while Cortex-M7 is in Debug mode
LPTIM4

LPTIM4 stop in debug

0 (B_0x0): Normal operation - LPTIM4 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - LPTIM4 is frozen while Cortex-M7 is in Debug mode
LPTIM5

LPTIM5 stop in debug

0 (B_0x0): Normal operation - LPTIM5 continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - LPTIM5 is frozen while Cortex-M7 is in Debug mode
RTC

RTC stop in debug

0 (B_0x0): Normal operation - RTC continues operating while the core is in Debug mode

1 (B_0x1): Stop in debug - RTC is frozen while Cortex-M7 is in Debug mode
IWDG

Independent watchdog for stop in debug

0 (B_0x0): Normal operation - watchdog continues counting while the core is in Debug mode

1 (B_0x1): Stop in debug - watchdog is frozen while Cortex-M7 is in Debug mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32