stm32 /stm32h7rs /STM32H7R /DCMIPP /DCMIPP_CMSR1

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Interpret as DCMIPP_CMSR1

PRVSYNC=B_0x0, P0CPTACT=B_0x0, PRHSYNC=B_0x0

Description

DCMIPP common status register 1

Fields

PRHSYNC	This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit of the DCMIPP_PRCR register, and cleared otherwise. When embedded synchronization codes are used the meaning of this bit is the following: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in the DCMIPP_PRCR register is set. 0 (B_0x0): Active line 1 (B_0x1): Synchronization between lines
PRVSYNC	This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit of the DCMIPP_PRCR register, and cleared otherwise. When embedded synchronization codes are used, the meaning of this bit is the following: In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in the DCMIPP_PRCR register is set. 0 (B_0x0): Active frame 1 (B_0x1): Synchronization between frames
P0CPTACT	Active frame capture (active from start-of-frame to frame complete) for Pipe0 0 (B_0x0): No capture currently active 1 (B_0x1): Capture currently active

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