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stm32 /stm32h7rs /STM32H7R /DCMIPP /DCMIPP_P0CPPM0AR2

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Interpret as DCMIPP_P0CPPM0AR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0M0A

Description

DCMIPP Pipe0 current pixel packer Memory0 address register 2

Fields

M0A

Memory0 address Base address of the current memory area 0, to whom data are written. It is assumed to be a multiple of 16, hence its bits 3:0 are always at 0x0.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32