stm32 /stm32h7rs /STM32H7R /DCMIPP /DCMIPP_P0FCTCR

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Interpret as DCMIPP_P0FCTCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FRATE 0 (B_0x0)CPTMODE 0 (B_0x0)CPTREQ

CPTREQ=B_0x0, CPTMODE=B_0x0, FRATE=B_0x0

Description

DCMIPP Pipe0 flow control configuration register

Fields

FRATE

Frame capture rate control These bits define the frequency of frame capture. They are meaningful only in Continuous grab mode, ignored in Snapshot mode.

0 (B_0x0): All frames are captured

1 (B_0x1): One out of two frames captured (50% bandwidth reduction)

2 (B_0x2): One out of four frames captured (75% bandwidth reduction)

3 (B_0x3): One out of eight frames captured (87% bandwidth reduction)

CPTMODE

Capture mode

0 (B_0x0): Continuous grab mode - The received data are transferred into the destination memory through the AXI master.

1 (B_0x1): Snapshot mode (single frame) - Once activated, the interface waits for the start of frame, and then transfers a single frame through the AXI master. At the end of the frame, the CPTACT bit is automatically reset.

CPTREQ

Capture requested When PIPEN = 1 and when the CPTREQ is set to 1 the pipe waits for the first VSync, and automatically starts a capture and sets CPTACT = 1 to mention it. In Snapshot mode the CPTREQ bit is automatically cleared at the start of the first received frame. In Continuous grab mode, the capture remains active and CPTREQ = 1 until the software clears CPTREQ: the capture stops and CPTACT is reset at the end of the ongoing frame. The DCMI and pipe configuration registers must be correctly programmed before enabling this bit.

0 (B_0x0): Capture not requested for next frame

1 (B_0x1): Capture requested for next frame

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