stm32 /stm32h7rs /STM32H7R /DCMIPP /DCMIPP_P0PPCR

Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs. LSB alignment.

0 (B_0x0): Aligns on LSB (and pads null bits on MSB), for backward compatibility with former DCMI.

1 (B_0x1): Aligns on MSB (and pads null bits on LSB), for better ease of software or GPU.

Byte select mode Modes 10 and 11 work only with EDM [2:0] = 000 into the DCMIPP_PRCR register.

0 (B_0x0): Interface captures all received data

1 (B_0x1): Interface captures 1 data out of 2

2 (B_0x2): Interface captures one byte out of four

3 (B_0x3): Interface captures two bytes out of four

Odd/even byte select (byte select start) This bit works in conjunction with BSM field (BSM different from 00)

0 (B_0x0): Interface captures the first data (byte or double byte) from the frame/line start, the second one is dropped

1 (B_0x1): Interface captures the second data (byte or double byte) from the frame/line start, the first one is dropped

Line select mode

0 (B_0x0): Interface captures all received lines

1 (B_0x1): Interface captures one line out of two

Odd/even line select (line select start) This bit works in conjunction with LSM field (LSM = 1).

0 (B_0x0): Interface captures first line after the frame start, second one is dropped

1 (B_0x1): Interface captures second line from the frame start, first one is dropped

Amount of capture completed lines for LINE event and interrupt

0 (B_0x0): Event after one line

1 (B_0x1): Event after two lines

2 (B_0x2): Event after four lines

3 (B_0x3): Event after eight lines

4 (B_0x4): Event after sixteen lines

5 (B_0x5): Event after 32 lines

6 (B_0x6): Event after 64 lines

7 (B_0x7): Event after 128 lines

Double buffer mode This bit is set and cleared by software.

0 (B_0x0): No double buffer mode activated. Pipe0 always dumps to memory address set by DCMIPP_P0PPM0AR1.

1 (B_0x1): Double buffer mode activated. Dump address location switches from DCMIPP_P0PPM0AR1 to DCMIPP_P0PPM0AR2 alternatively on each frame.