LNGF=B_0x0
DLYB configuration register
| SEL | Phase for the output clock. These bits can only be written when SEN = 1. Output clock phase = input clock + SEL[3:0] x unit delay |
| UNIT | Delay of a unit delay cell. These bits can only be written when SEN = 1. Unit delay = initial delay + UNIT[6:0] x delay step |
| LNG | Delay line length value These bits reflect the 12 unit delay values sampled at the rising edge of the input clock. The value is only valid when LNGF = 1. |
| LNGF | Length valid flag This flag indicates when the delay line length value contained in LNG[11:0] is valid after UNIT[6:0] bits changed. 0 (B_0x0): Length value in LNG is not valid. 1 (B_0x1): Length value in LNG is valid. |