stm32 /stm32h7rs /STM32H7R /DMA2D /DMA2D_FGPFCCR

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Interpret as DMA2D_FGPFCCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CM0 (B_0x0)CCM 0 (START)START 0CS0 (B_0x0)AM0 (B_0x0)CSS0 (B_0x0)AI 0 (B_0x0)RBS 0ALPHA

RBS=B_0x0, CSS=B_0x0, AM=B_0x0, AI=B_0x0, CCM=B_0x0, CM=B_0x0

Description

DMA2D foreground PFC control register

Fields

CM

Color mode These bits defines the color format of the foreground image. Others: Reserved

0 (B_0x0): ARGB8888

1 (B_0x1): RGB888

2 (B_0x2): RGB565

3 (B_0x3): ARGB1555

4 (B_0x4): ARGB4444

5 (B_0x5): L8

6 (B_0x6): AL44

7 (B_0x7): AL88

8 (B_0x8): L4

9 (B_0x9): A8

10 (B_0xA): A4

11 (B_0xB): YCbCr

CCM

CLUT color mode This bit defines the color format of the CLUT.

0 (B_0x0): ARGB8888

1 (B_0x1): RGB888

START

Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: at the end of the transfer when the transfer is aborted by the user by setting ABORT in DMA2D_CR when a transfer error occurs when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)

CS

CLUT size These bits define the size of the CLUT used for the foreground image. The number of CLUT entries is equal to CS[7:0] + 1.

AM

Alpha mode These bits select the alpha channel value to be used for the foreground image. Others: Reserved

0 (B_0x0): No modification of the foreground image alpha channel value

1 (B_0x1): Replace original foreground image alpha channel value by ALPHA[7: 0]

2 (B_0x2): Replace original foreground image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value

CSS

Chroma subsampling These bits define the chroma subsampling mode for YCbCr color mode. Others: Reserved

0 (B_0x0): 4:4:4 (no chroma subsampling)

1 (B_0x1): 4:2:2

2 (B_0x2): 4:2:0

AI

Alpha inverted This bit inverts the alpha value.

0 (B_0x0): Regular alpha

1 (B_0x1): Inverted alpha

RBS

Red/Blue swap This bit allows to swap Red and Blue to support BGR or ABGR color formats.

0 (B_0x0): Regular mode (RGB or ARGB)

1 (B_0x1): Swap mode (BGR or ABGR)

ALPHA

Alpha value These bits define a fixed alpha channel value which can replace the original alpha value, or be multiplied by the original alpha value, according to the alpha mode selected through AM[1:0] in this register.

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