AI=B_0x0, SB=B_0x0, RBS=B_0x0, CM=B_0x0
DMA2D output PFC control register
| CM | Color mode These bits define the color format of the output image. Others: Reserved 0 (B_0x0): ARGB8888 1 (B_0x1): RGB888 2 (B_0x2): RGB565 3 (B_0x3): ARGB1555 4 (B_0x4): ARGB4444 |
| SB | Swap bytes When this bit is set, the bytes in the output FIFO are swapped two by two. The number of pixels per line (PL) must be even, and the output memory address (OMAR) must be even. 0 (B_0x0): Bytes in regular order in the output FIFO 1 (B_0x1): Bytes swapped two by two in the output FIFO |
| AI | Alpha Inverted This bit inverts the alpha value. 0 (B_0x0): Regular alpha 1 (B_0x1): Inverted alpha |
| RBS | Red/Blue swap This bit allows to swap Red and Blue to support BGR or ABGR color formats. 0 (B_0x0): Regular mode (RGB or ARGB) 1 (B_0x1): Swap mode (BGR or ABGR) |