TRGTMODSEL0=B_0x0, PPSCMD=B_0x0
PPS control register
| PPSCMD | Flexible PPS Output (eth_ptp_pps_out) Control Programming these bits with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The software should ensure that these bits are programmed only when they are all zero. The following list describes the values of PPSCMD0: This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS Width Register. This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by the ‘Stop Pulse train at time’ or ‘Stop Pulse Train immediately’ commands. This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time. This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD[3:0] = 0010) after the time programmed in the Target Time registers elapses. This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD[3:0] = 0010). This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command. 0111 to 1111: Reserved, must not be used 0 (B_0x0): No Command 1 (B_0x1): START Single Pulse. 2 (B_0x2): START Pulse Train. 3 (B_0x3): Cancel START. 4 (B_0x4): STOP Pulse Train at time. 5 (B_0x5): STOP Pulse Train immediately. 6 (B_0x6): Cancel STOP Pulse train. |
| PPSEN0 | Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD[3:0]. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode). |
| TRGTMODSEL0 | Target Time Register Mode for PPS Output This field indicates the Target Time registers (MAC registers 96 and 97) mode for PPS output signal: 0 (B_0x0): Target Time registers are programmed only for generating the interrupt event. 1 (B_0x1): Reserved, must not be used 2 (B_0x2): Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. 3 (B_0x3): Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. |