MR24=B_0x0, MR4=B_0x0, MR14=B_0x0, MR23=B_0x0, MR3=B_0x0, MR9=B_0x0, MR19=B_0x0, MR5=B_0x0, MR17=B_0x0, MR20=B_0x0, MR1=B_0x0, MR30=B_0x0, MR11=B_0x0, MR31=B_0x0, MR25=B_0x0, MR13=B_0x0, MR16=B_0x0, MR22=B_0x0, MR0=B_0x0, MR15=B_0x0, MR6=B_0x0, MR28=B_0x0, MR29=B_0x0, MR18=B_0x0, MR7=B_0x0, MR21=B_0x0, MR8=B_0x0, MR26=B_0x0, MR27=B_0x0, MR12=B_0x0, MR10=B_0x0, MR2=B_0x0
EXTI interrupt mask register
| MR0 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR1 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR2 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR3 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR4 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR5 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR6 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR7 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR8 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR9 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR10 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR11 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR12 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR13 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR14 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR15 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR16 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR17 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR18 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR19 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR20 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR21 | CPU interrupt mask on configurable event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR22 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR23 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR24 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR25 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR26 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR27 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR28 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR29 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR30 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR31 | CPU interrupt mask on direct event input x 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |