MR32=B_0x0, MR53=B_0x0, MR39=B_0x0, MR41=B_0x0, MR33=B_0x0, MR44=B_0x0, MR55=B_0x0, MR40=B_0x0, MR49=B_0x0, MR51=B_0x0, MR56=B_0x0, MR57=B_0x0, MR42=B_0x0, MR34=B_0x0, MR47=B_0x0, MR37=B_0x0, MR59=B_0x0, MR43=B_0x0, MR54=B_0x0, MR38=B_0x0, MR46=B_0x0, MR45=B_0x0, MR50=B_0x0, MR35=B_0x0, MR52=B_0x0, MR58=B_0x0, MR48=B_0x0, MR36=B_0x0
EXTI interrupt mask register
| MR32 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR33 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR34 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR35 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR36 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR37 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR38 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR39 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR40 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR41 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR42 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR43 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR44 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR45 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR46 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR47 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR48 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR49 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR50 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR51 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR52 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR53 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR54 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR55 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR56 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR57 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR58 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |
| MR59 | CPU interrupt mask on direct event input i 0 (B_0x0): Interrupt request from line x is masked 1 (B_0x1): Interrupt request from line x is unmasked |