RegViz: Visualize FLASH

stm32 /stm32h7rs /STM32H7R /FLASH /FLASH_IER

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Interpret as FLASH_IER

CRCENDIE=B_0x0, PGSERRIE=B_0x0, RDSERRIE=B_0x0, CRCRDERRIE=B_0x0, DBECCERRIE=B_0x0, SNECCERRIE=B_0x0, STRBERRIE=B_0x0, EOPIE=B_0x0, OBLERRIE=B_0x0, WRPERRIE=B_0x0, INCERRIE=B_0x0

Description

FLASH interrupt enable register

Fields

EOPIE	End-of-program interrupt control bit 0 (B_0x0): No interrupt is generated when OEPF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when OEPF bit is set in FLASH_ISR register
WRPERRIE	Write protection error interrupt enable bit 0 (B_0x0): No interrupt is generated when WRPERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when WRPERRF bit is set in FLASH_ISR register
PGSERRIE	Programming sequence error interrupt enable bit 0 (B_0x0): No interrupt is generated when PGSERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when PGSERRF bit is set in FLASH_ISR register
STRBERRIE	Strobe error interrupt enable bit 0 (B_0x0): No interrupt is generated when STRBERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when STRBERRF bit is set in FLASH_ISR register
OBLERRIE	Option byte loading error interrupt enable bit 0 (B_0x0): No interrupt is generated when OBLERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when OBLERRF bit is set in FLASH_ISR register
INCERRIE	Inconsistency error interrupt enable bit 0 (B_0x0): No interrupt is generated when INCERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when INCERRF bit is set in FLASH_ISR register
RDSERRIE	Read security error interrupt enable bit 0 (B_0x0): No interrupt is generated when RDSERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when RDSERRF bit is set in FLASH_ISR register
SNECCERRIE	ECC single correction error interrupt enable bit 0 (B_0x0): No interrupt is generated when SNECCERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when SNECCERRF bit is set in FLASH_ISR register
DBECCERRIE	ECC double detection error interrupt enable bit 0 (B_0x0): No interrupt is generated when DBECCERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when DBECCERRF bit is set in FLASH_ISR register
CRCENDIE	CRC end of calculation interrupt enable bit 0 (B_0x0): No interrupt is generated when CRCEN bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when CRCEN bit is set in FLASH_ISR register
CRCRDERRIE	CRC read error interrupt enable bit 0 (B_0x0): No interrupt is generated when CRCRDERRF bit is set in FLASH_ISR register 1 (B_0x1): An interrupt is generated when CRCRDERRF bit is set in FLASH_ISR register

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