PGSERRF=B_0x0, WRPERRF=B_0x0, EOPF=B_0x0, CRCENDF=B_0x0, INCERRF=B_0x0, OBLERRF=B_0x0, SNECCERRF=B_0x0, DBECCERRF=B_0x0, CRCRDERRF=B_0x0, STRBERRF=B_0x0, RDSERRF=B_0x0
FLASH interrupt status register
| EOPF | End-of-program flag This bit is set when a programming operation completes. An interrupt is generated if the EOPIE is set. It is not necessary to reset EOPF before starting a new operation. Setting EOPF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No programming operation completed 1 (B_0x1): A programming operation completed |
| WRPERRF | Write protection error flag This bit is set when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set. Setting WRPERRF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No write protection error occurred 1 (B_0x1): A write protection error occurred |
| PGSERRF | Programming sequence error flag This bit is set when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set. Setting PGSERRF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No sequence error occurred 1 (B_0x1): Asequence error occurred |
| STRBERRF | Strobe error flag This bit is set when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set. Setting STRBERRF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No strobe error occurred 1 (B_0x1): Astrobe error occurred |
| OBLERRF | Option byte loading error flag This bit is set when an error is found during the option byte loading sequence. An interrupt is generated if OBLERRIE is set. Setting OBLERRF bit in the FLASH_ICR register clears this bit. 0 (B_0x0): No error found during option byte loading sequence 1 (B_0x1): Some errors found during option byte loading sequence |
| INCERRF | Inconsistency error flag This bit is set when a inconsistency error occurs. An interrupt is generated if INCERRIE is set. Setting INCERRF bit in the FLASH_ICR register clears this bit. 0 (B_0x0): No inconsistency error occurred 1 (B_0x1): A inconsistency error occurred |
| RDSERRF | Read security error flag This bit is set when a read security error occurs (read access to hide protected area with incorrect hide protection level). An interrupt is generated if RDSERRIE is set. Setting RDSERRF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No security error occurred 1 (B_0x1): A security error occurred |
| SNECCERRF | ECC single error flag This bit is set when an ECC single correction error occurs during a read operation. An interrupt is generated if SNECCERRIE is set. Setting SNECCERRF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No ECC single correction error occurred 1 (B_0x1): ECC single correction error occurred |
| DBECCERRF | ECC double error flag This bit is set when an ECC double detection error occurs during a read operation. An interrupt is generated if DBECCERRIE is set. Setting DBECCERRF bit in FLASH_ICR register clears this bit. 0 (B_0x0): No ECC double detection error occurred 1 (B_0x1): ECC double detection error occurred |
| CRCENDF | CRC end flag This bit is set when the CRC computation has completed. An interrupt is generated if CRCENDIE is set. It is not necessary to reset CRCEND before restarting CRC computation. Setting CRCENDF bit in FLASH_ICR register clears this bit. 0 (B_0x0): CRC computation not complete 1 (B_0x1): CRC computation complete |
| CRCRDERRF | CRC read error flag This bit is set when a word is found read protected during a CRC operation. An interrupt is generated if CRCRDIE is set. Setting CRCRDERRF bit in FLASH_ICR register clears this bit. This flag is valid only when CRCEND bit is set. 0 (B_0x0): No protected area detected inside addresses read by CRC 1 (B_0x1): At least one protected area has been detected inside address read by CRC. As a result CRC result is very likely incorrect. |