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stm32 /stm32h7rs /STM32H7R /FLASH /FLASH_OBW2SRP

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Interpret as FLASH_OBW2SRP

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ITCM_AXI_SHARE 0DTCM_AXI_SHARE 0 (ECC_ON_SRAM)ECC_ON_SRAM 0 (I2C_NI3C)I2C_NI3C

Description

FLASH option byte word 2 status register programming

Fields

ITCM_AXI_SHARE

ITCM AXI share programming Write to change corresponding bits in FLASH_OBW2SR register. Bit 2 should be kept to 0: ITCM_AXI_SHARE: = 000 or 011: ITCM 64 Kbytes ITCM_AXI_SHARE = 001: ITCM 128 Kbytes ITCM_AXI_SHARE = 010: ITCM 192 Kbytes
DTCM_AXI_SHARE

DTCM AXI share programming Write to change corresponding bits in the FLASH_OBW2SR register. Bit 2 should be kept to 0: DTCM_AXI_SHARE = 000 or 011: DTCM 64 Kbytes DTCM_AXI_SHARE = 001: DTCM 128 Kbytes DTCM_AXI_SHARE = 010: DTCM 192 Kbytes
ECC_ON_SRAM

ECC on SRAM programming Write to change corresponding bit in FLASH_OBW2SR register.
I2C_NI3C

I2C Not I3C Write to change corresponding bit in FLASH_OBW2SR register.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32