stm32 /stm32h7rs /STM32H7R /FMC /FMC_BTR4

Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 109 to Figure 121), used in SRAMs, ROMs and asynchronous NOR flash: … For each access mode address setup phase duration, please refer to the respective figure (refer to Figure 109 to Figure 121). Note: In synchronous accesses, this value is dont care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

0 (B_0x0): ADDSET phase duration = 0 fmc_ker_ck clock cycle

15 (B_0xF): ADDSET phase duration = 15 fmc_ker_ck clock cycles (default value after reset)

Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 109 to Figure 121), used in mode D or multiplexed accesses: … For each access mode address-hold phase duration, please refer to the respective figure (Figure 109 to Figure 121). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

1 (B_0x1): ADDHLD phase duration =1 fmc_ker_ck clock cycle

2 (B_0x2): ADDHLD phase duration = 2 fmc_ker_ck clock cycle

15 (B_0xF): ADDHLD phase duration = 15 fmc_ker_ck clock cycles (default value after reset)

Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 109 to Figure 121), used in asynchronous accesses: … For each memory type and access mode data-phase duration, please refer to the respective figure (Figure 109 to Figure 121). Example: Mode1, write access, DATAST = 1: Data-phase duration = DATAST+1 = 1 x fmc_ker_ck clock cycles. Note: In synchronous accesses, this value is dont care.

1 (B_0x1): DATAST phase duration = 1 fmc_ker_ck clock cycles

2 (B_0x2): DATAST phase duration = 2 fmc_ker_ck clock cycles

255 (B_0xFF): DATAST phase duration = 255 fmc_ker_ck clock cycles (default value after reset)

Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to-write) transaction. This delay allows to match the minimum time between consecutive transactions (t_EHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (t_EHQZ). The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D. In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed and D modes. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for muxed and D modes. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for muxed and D modes. An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different for the case of read. Two consecutive synchronous reads (burst or single) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to different static bank. A synchronous write (burst or single) access and a synchronous read from the same or a different bank. …

0 (B_0x0): BUSTURN phase duration = 0 fmc_ker_ck clock cycle added

15 (B_0xF): BUSTURN phase duration = 15 x fmc_ker_ck clock cycles added (default value after reset)

Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of fmc_ker_ck cycles: In asynchronous NOR flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section 23.7.5: Synchronous transactions for FMC_CLK divider ratio formula)

0 (B_0x0): FMC_CLK period = 1 x fmc_ker_ck period

1 (B_0x1): FMC_CLK period = 2 fmc_ker_ck periods

2 (B_0x2): FMC_CLK period = 3 fmc_ker_ck periods

15 (B_0xF): FMC_CLK period = 16 fmc_ker_ck periods (default value after reset)

(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), these bits define the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in fmc_ker_ck periods, but in FMC_CLK periods. For asynchronous access, this value is don’t care.

0 (B_0x0): Data latency of 2 FMC_CLK clock cycles for first burst access

15 (B_0xF): Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset)

Access mode These bits specify the Asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

0 (B_0x0): access mode A

1 (B_0x1): access mode B

2 (B_0x2): access mode C

3 (B_0x3): access mode D