ATTHIZ=B_0x0, ATTSET=B_0x0
Attribute memory space timing registers
| ATTSET | Attribute memory setup time These bits define the number of fmc_ker_ck (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND flash read or write access to attribute memory space: 0 (B_0x0): 1 x fmc_ker_ck cycle 254 (B_0xFE): 255 x fmc_ker_ck cycles 255 (B_0xFF): reserved. |
| ATTWAIT | Attribute memory wait time These bits define the minimum number of x fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), for NAND flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck: 1 (B_0x1): 2 x fmc_ker_ck cycles (+ wait cycle introduced by deassertion of NWAIT) 254 (B_0xFE): 255 x fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT) 255 (B_0xFF): reserved. |
| ATTHOLD | Attribute memory hold time These bits define the number of fmc_ker_ck clock cycles during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND flash read or write access to attribute memory space: 1 (B_0x1): 1 x fmc_ker_ck cycle 254 (B_0xFE): 254 x fmc_ker_ck cycles 255 (B_0xFF): reserved. |
| ATTHIZ | Attribute memory data bus Hi-Z time These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept in Hi-Z after the start of a NAND flash write access to attribute memory space on socket. Only valid for writ transaction: 0 (B_0x0): 0 x fmc_ker_ck cycle 254 (B_0xFE): 254 x fmc_ker_ck cycles 255 (B_0xFF): reserved. |