MEMSET=B_0x0, MEMHOLD=B_0x0, MEMHIZ=B_0x0
Common memory space timing register
| MEMSET | Common memory x setup time These bits define the number of fmc_ker_ck (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND flash read or write access to common memory space: 0 (B_0x0): fmc_ker_ck cycles 254 (B_0xFE): 255 x fmc_ker_ck cycles |
| MEMWAIT | Common memory wait time These bits define the minimum number of fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), for NAND flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck: 1 (B_0x1): x fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT) 254 (B_0xFE): 255 x fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT) |
| MEMHOLD | Common memory hold time These bits define the number of fmc_ker_ck clock cycles for write accesses and fmc_ker_ck+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND flash read or write access to common memory space: 0 (B_0x0): reserved. 1 (B_0x1): 1 fmc_ker_ck cycle for write access / 3 fmc_ker_ck cycle for read access 254 (B_0xFE): 254 fmc_ker_ck cycles for write access / 257 fmc_ker_ck cycles for read access 255 (B_0xFF): reserved. |
| MEMHIZ | Common memory x data bus Hi-Z time These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept Hi-Z after the start of a NAND flash write access to common memory space. This is only valid for write transactions: 0 (B_0x0): 0 x fmc_ker_ck cycle 254 (B_0xFE): 254 x fmc_ker_ck cycles 255 (B_0xFF): reserved. |