stm32 /stm32h7rs /STM32H7R /FMC /FMC_SDCR2

Number of column address bits These bits define the number of bits of a column address.

0 (B_0x0): 8 bits

1 (B_0x1): 9 bits

2 (B_0x2): 10 bits

3 (B_0x3): 11 bits.

Number of row address bits These bits define the number of bits of a row address.

0 (B_0x0): 11 bit

1 (B_0x1): 12 bits

2 (B_0x2): 13 bits

3 (B_0x3): reserved.

Memory data bus width. These bits define the memory device width.

0 (B_0x0): 8 bits

1 (B_0x1): 16 bits

2 (B_0x2): 32 bits

3 (B_0x3): reserved.

Number of internal banks This bit sets the number of internal banks.

0 (B_0x0): Two internal Banks

1 (B_0x1): Four internal Banks

CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles

0 (B_0x0): reserved.

1 (B_0x1): 1 cycle

2 (B_0x2): 2 cycles

3 (B_0x3): 3 cycles

Write protection This bit enables Write mode access to the SDRAM bank.

0 (B_0x0): Write accesses allowed

1 (B_0x1): Write accesses ignored

SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only.

0 (B_0x0): SDCLK clock disabled

2 (B_0x2): SDCLK period = 2 x fmc_ker_ck periods

3 (B_0x3): SDCLK period = 3 x fmc_ker_ck periods

Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only.

0 (B_0x0): single read requests are not managed as bursts

1 (B_0x1): single read requests are always managed as bursts

Read pipe These bits define the delay, in fmc_ker_ck clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.

0 (B_0x0): No fmc_ker_ck clock cycle delay

1 (B_0x1): One fmc_ker_ck clock cycle delay

2 (B_0x2): Two fmc_ker_ck clock cycle delay

3 (B_0x3): reserved.