UB2=B_0x0, UB1=B_0x0, UT1=B_0x0, UT2=B_0x0, USA=B_0x0, UT3=B_0x0, UDA=B_0x0, ULL=B_0x0
HPDMA channel 14 alternate linked-list address register
| LA | pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. |
| ULL | Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxLLR update 1 (B_0x1): HPDMA_CxLLR update |
| UB2 | Update HPDMA_CxBR2 from memory This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxBR2 update 1 (B_0x1): HPDMA_CxBR2 update |
| UT3 | Update HPDMA_CxTR3 from memory This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxTR3 update 1 (B_0x1): HPDMA_CxTR3 update |
| UDA | Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxDAR update 1 (B_0x1): HPDMA_CxDAR update |
| USA | update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxSAR update 1 (B_0x1): HPDMA_CxSAR update |
| UB1 | Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 0 (B_0x0): no HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any link transfer) 1 (B_0x1): HPDMA_CxBR1 update |
| UT2 | Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxTR2 update 1 (B_0x1): HPDMA_CxTR2 update |
| UT1 | Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer. 0 (B_0x0): no HPDMA_CxTR1 update 1 (B_0x1): HPDMA_CxTR1 update |